Method and circuit arrangement for synchronizing a function unit with a predetermined clock frequency

ABSTRACT

A receiver is synchronized with a first clock frequency or signal of a transmitter for the proper reception of transmitted and received signals, such as data carrying signals (DS). The first clock frequency is for example a carrier frequency. A local oscillator generates a second clock frequency or signal in the receiver. Cycles or impulses of the second clock signal are counted between predetermined flanks of the received signal (DS) to provide a count (N). Based on the second clock signal and the count (N) a first ratio (TV) is provided that represents a first ratio between the first clock frequency or signal and the second clock frequency or signal. The first ratio is compared with a predetermined or given second ratio (TV) to provide a comparing result. The predetermined second ratio is then updated in response to the comparing result to provide an updated ratio (TV′). The present circuit is constructed to perform these steps.

PRIORITY CLAIM

This application is based on and claims the priority under 35 U.S.C.§119 of German Patent Application 10 2004 006 398.2, filed on Feb. 10,2004, the entire disclosure of which is incorporated herein byreference.

FIELD OF THE INVENTION

A function unit such as a receiver circuit and/or a signal selectioncircuit or the like is synchronized with a clock frequency of a receivedsignal, particularly a data information carrying signal. The inventionalso relates to a circuit arrangement for performing the present method.These function units or circuits are preferably part of an integratedcircuit.

BACKGROUND INFORMATION

The transmission of serial data at a determined data transmission rateis quite common in a multitude of technical areas. For example, a datasource such as a microcontroller, may transmit such serial data at adetermined first clock signal or frequency through a unidirectional dataconnection. Such a data connection may, for example, be a single wirebus without any response capability. The transmitted data are receivedby a receiver such as an integrated circuit (IC) and are to be evaluatedwithin the receiver. Customarily a transmitter as the source of the datasignals and the receiver do not have a common synchronizing clock.Therefore, the receiver must itself synchronize to the transmitter forrecovering the first clock signal that is contained within the serialdata. Such clock signal retrieval is necessary in order to correctlyinterrogate the data in a bit-by-bit fashion.

Normally the signal rate of the first clock signal is represented by afraction of a local oscillator frequency or local oscillator clock rateof the receiver, whereby the local oscillator clock rate is provided asa second clock rate or frequency. Ideally, the first and second clockfrequencies should be the same, whereby synchronization is automaticallyassured. In practice the local oscillator clock rate is determined, as arule, internally of the integrated circuit by a local (RC)-oscillatorhaving a clock frequency that is known only within certain limits. Withthe beginning of a starting bit of a data signal a counter is started tocount. The respective count is incremented with each clock period orcycle, that is, with each internal or local clock pulse. The counter isreset to zero and then begins to count again when a count is reachedthat corresponds to a division ratio between the first data clock signalof the received signal and the second local oscillator clock signal orfirst and second clock signal frequencies. This resetting corresponds,when a correct synchronization is achieved, exactly to the beginning ofthe next data bit. Exactly at the center of the division, that is in thecenter of the data bit, the bus level is interrogated and thus therespective bit read-out. A second counter terminates this operation whena certain number of bits has been read.

Conventionally, there is the basic problem that the reading operationfails due to an erroneous synchronization between transmitter andreceiver. A failed read-out can have grave adverse effects. Particularlyin connection with uni-directional transmission media, there is noresponse possibility. Therefore, the receiver cannot request a knownsynchronization signal for a renewed follow-up synchronization duringthe transmission. Furthermore, it is not possible to make a renewedrequest for a date information that has been erroneously recognized. Anerroneous synchronization means in this context that the divider orrather the division ratio deviates from a correct value either upwardlyor downwardly. As a result, the counter is not reset as required, namelyat the end of a data bit. Rather, the counter is reset either somewhattoo early or somewhat too late. Correspondingly, the interrogation ofthe bus level does not take place at the center of a bit. To makematters worse, the up or down shifts accumulate as the number of bits tobe interrogated increases. When the last bit of a sequence of bits isstill correctly interrogated, the system is tolerant relative to anerroneous synchronization. Otherwise, double interrogations may benecessary and/or individual bits may be skipped. Further, the secondclock frequency of the receiver is known only within certain limits suchas ±10% of a rated clock frequency. Such tolerances are necessary due tomanufacturing conditions. As a result, it is not possible to set a fixeddivider or division ratio to achieve a constant, correct synchronizationof the transmitter and the receiver forming together a system.

In order to achieve a certain synchronization between a transmitter anda receiver it has been suggested in conventional data transmissionsystems such as the LIN-bus (Local Interconnect Network) to transmit aso-called synchronization field. This synchronization field istransmitted at uniform time spacings prior to each data transmission andsubsequent to a synchronization pause having a predetermined minimalduration. Reference is made in this connection to “LIN ProtocolSpecification”, Revision 1.1 2000. The suggested system has theparticular disadvantage that only a limited data transmission rate isavailable for useful data due to the necessary transmissioninterruptions. Furthermore, a single transmission error during thesynchronization field, leads to a faulty synchronization during thefollowing data transmission.

Another disadvantage of the above system is seen in that the clockfrequency of the receiver can change during the operation, for exampledue to temperature influences. Thus, there is the possibility that, eventhough a single synchronization was correct, a following evaluation maybe erroneous, nevertheless.

OBJECTS OF THE INVENTION

In view of the foregoing it is the aim of the invention to achieve thefollowing objects singly or in combination:

-   -   to provide a method and circuit arrangement for performing the        method for avoiding the above outlined disadvantages of the        prior art;    -   to prevent errors occurring at points of time from completely        destroying a prior synchronization;    -   to provide a method and circuit arrangement that has a certain        tolerance against errors in the synchronization;    -   to perform the synchronization during the data transmission so        that the entire data rate is available for a useful signal        transmission because sending of separate synchronization        sequences or fields is avoided;    -   to make sure that occurring errors automatically compensate each        other; and    -   to assure, even for single wire transmission busses, a certain        synchronization that is not sensitive to transmission        disturbances, such as spikes in the transmission signal, nor to        temperature influences.

The invention further aims to avoid or overcome the disadvantages of theprior art, and to achieve additional advantages, as apparent from thepresent specification. The attainment of these objects is, however, nota required limitation of the claimed invention.

SUMMARY OF THE INVENTION

The above objects have been achieved in a method in which the followingsteps are performed. The cycles of a local oscillator signal having asecond clock frequency generated by a local oscillator in the functionunit such as a data receiver are counted between predetermined flanks ofthe received data carrying signal having a first clock frequency toprovide a respective count or count value. Then the clock signalfrequency of the internal oscillator is divided by the count to providea ratio between the received first signal clock and the internaloscillator second clock signal. The so achieved ratio is then comparedwith a predetermined ratio or division ratio that is given for thefunction unit such as a data receiver. Then, the predetermined divisionratio is adapted or updated in response to the comparing result toprovide an updated ratio (TV′) for use as the next predetermined ratio.

The above method is performed according to the invention by a circuitarrangement comprising the following features. A counter or counters areprovided for determining a count of clocks or clock cycles of aninternal oscillator of the function unit between predetermined flanks ofthe received signal. These predetermined flanks may be falling or risingflanks. Determination means are provided for determining a ratio betweenthe received signal clock and the local oscillator clock. A comparatoris provided for comparing the just mentioned ratio with a predeterminedratio of the respective function unit. An adapter then updates or adaptsthe predetermined division ratio depending on the result of thecomparing to provide an updated ratio (TV′) for use as the predeterminednext ratio.

Thus, according to the invention the synchronization is performed duringthe current data transmission, whereby the synchronization result, morespecifically an ascertained ratio is not used directly and absolutely,but rather is used only for adapting or updating the latestpredetermined ratio in accordance with the comparing. In this manner itis assured that a certain or accurate synchronization is achieved at theend of a data sequence and that manufacturing limitations or conditionsand/or temperature depending tolerances or changes of the internaloscillator frequency are compensated. Another advantage of the inventionis seen in that the entire data rate is available for the transmissionof useful signals rather than for the transmission of a synchronizingfield. Thus, the transmission of separate synchronization frequencies orfields is avoided. Spikes in the transmitted signal are alsocompensated.

The adaptation or updating of the division ratio simply referred to asratio is preferably performed in accordance with the following rules:TV′=TV+1, for N/2>TV;TV′=TV−1, for N/2<TV; andTV′=TV, for N/2=TV,wherein TV is the initial predetermined division ratio referred tosimply as ratio, wherein TV′ is the adapted or updated ratio and N isthe above mentioned count or count value. The invention achieves acurrent or gradual adaptation or updating of the synchronization so thatany individual transmission error cannot lead to a completely erroneousdivision ratio, thereby limiting the error to a value of about 1. Such asmall error is compensated during the next correct transmission.Correspondingly, the adapting or updating components of the presentcircuit arrangement are constructed to operate in accordance with theabove stated rules.

The above mentioned counting of the clocks or cycles of the internaloscillator signal is preferably performed between two falling flanks ofthe received signal. However, counting between two rising flanks is alsopossible. The counter or counters used according to the invention arecorrespondingly equipped to count the clocks or cycles of the internaloscillator between two rising or between two falling flanks. As aresult, the synchronization is constantly or always performed during thedata transmission at a point when the sequence “1010” occurs in thedata. No separate synchronization signal is necessary for this purpose.When the count is alternatively performed between two rising flanks orthe received signal, the data sequence would be “0101”.

Generally speaking, the bit length is ascertained with the aid of twoequal signal flanks or impulse flanks either rising or falling. In thismanner errors compensate each other automatically where such errorscould occur when the bit length of a low or high bit are measured outdifferently due to the analog conditions. Sources for the abovementioned faults or errors may be as follows.

First, the comparator threshold does not lie exactly at the center ofthe analog signal level.

Second, the comparator may have a hysteresis characteristic, that isasymmetric.

Third, the rising and falling times of the analog bus signal differ fromone another.

Fourth, the bus signal itself has different low bit and high bit lengthsor durations.

Fifth, the comparator has different slew rates for a low/high or ahigh/low transition.

Sixth, the comparator has different time delay durations orcharacteristics, depending on external conditions.

According to a further embodiment of the method according to theinvention, an adapted or updated division ratio is stored for subsequentuse. The storing takes place when the second predetermined signal flankis reached and the respective count is reset, whereupon the adaptedratio is stored as that ratio which is to be determined. The circuitarrangement according to the invention comprises for this purposememories for storing the adapted or updated ratio as a new predeterminedratio.

A particular preferred embodiment of the invention provides that noadaptation or updating of the ratio takes place when the count isoutside of a certain validity range. In other words, when the countexceeds a determined maximum value or when it is smaller than adetermined minimal value, no updating of the division ratio takes place.For this purpose the comparator and/or the adaptation unit of thepresent circuit is constructed to prevent such an adaptation in responseto the respective count being outside of the predetermined certainvalidity range. This feature of the invention has the advantage thatlocal transmission errors on the bus are not used for determining theratio. Such transmission errors may, for example involve spikes or thelike in the transmitted signal. Moreover, an overflow of the counter isprevented. Such prevention is advantageous because adverse consequencesmay follow in that a wrong count is interpreted after an overflow asbeing valid while it is not valid. An invalid count would endanger theentire synchronization when the data transmission is repeated.

BRIEF DESCRIPTION OF THE DRAWINGS

In order that the invention may be clearly understood, it will now bedescribed in connection with example embodiments thereof, with referenceto the accompanying drawings, wherein:

FIG. 1 illustrates a block circuit diagram of the circuit arrangementaccording to the invention;

FIG. 2 shows basic wave forms or impulses regarding the validity rangeof a ratio adaptation or updating according to the invention includingavoiding a counter overflow when performing the present method; and

FIG. 3 shows a flow diagram illustrating the performance of the presentmethod.

DETAILED DESCRIPTION OF A PREFERRED EXAMPLE EMBODIMENT AND OF THE BESTMODE OF THE INVENTION

FIG. 1 shows in the block diagram the basic construction of an apparatusor circuit arrangement 1 according to the invention. The circuitarrangement 1 has an input 2 to receive a serial data signal DS having adata clock DT constituting a first clock signal with a first clocksignal frequency. The circuit has an output 3 for providing outputsignals DS of interrogated data or data bits in the form of an outputsignal AS. The data interrogation is performed by an interrogator orreceiver circuit 4 positioned between the input 2 and the output 3 andconnected to the input and output.

A counter 5 such as a down counter has a first input connected to theinput 2 of the circuit arrangement 1 to receive the signal DS. Thecounter 5 also has a second input connected to a local or internaloscillator 7 and a memory 6, preferably as part of the counter connectedwith a third counter input to a comparator BA of a computer 8. Thememory 6 temporarily stores counts or count values N and ratio values TVfor influencing the counter 5 and the interrogation unit 4 connected toan output of the counter 5. The counter 5 receives the clock impulses ofthe internal oscillator 7 which is:, for example an RC-oscillator with anominal or rated second clock frequency of 400 kHz (±10%). The presentcircuit arrangement can also be equipped with an up counter forperforming the present method.

The counter 6 is operatively connected to the computer 8 which in turnfunctions for adapting or updating the ratio values TV as a function ofthe output signal of the counter. This counter output signal representsthe count N of the counter 5. A signal divider 9 may be optionallyconnected between the counter 5 and the computer 8. This divider 9 isconstructed to divide the count number N by 2.

The box 9 representing the dividing circuit is shown in brackets in FIG.1 to indicate that a separate divider is optional because this functioncan be performed by the computer 8. For this purpose the computer 8 isequipped to perform the division of the count by 2.

The present circuit arrangement 1 shown in FIG. 1 functions as follows.In order to determine the ratio TV between the local oscillator clocksignal IT and the data clock signal DT, the number N of the clockimpulses of the local oscillator 7 is counted between two falling flanksof the received data signal DS. More specifically, the counter 5 countsthe pulses of the signal sequence “1010”. In this context “1” is thehigh level and “0” is the low level of the received data signal DS.Ascertaining a clock count N between a falling signal flank and a risingsignal flank indicated by a signal sequence “1001”, could lead to errorsin case a comparing threshold value is wrong in the interrogator circuit4 connected to the data transmitting bus, not shown. As mentioned above,the evaluation is also possible by counting between two rising flanks(“0101”) of the transmitted and received data signal DS. In thefollowing text the performance of the present method is described withreference to counting the clock count or count value between two fallingsignal flanks of the received data signal DS. However, it is to beunderstood, that the invention is not limited to this type of counting.

The counter is started each time a falling flank of a received datasignal DS occurs on the data bus connected to the input 2. The counterkeeps counting following each local oscillator clock or impulse, morespecifically following each past local oscillator clock or impulse(DT⁻¹) until the next following falling flank of the data signal DSstops the counter 5. Thus, the count N corresponds to the number oflocal oscillator clocks or clock cycles between two falling flanks ofthe data signal DS.

The count value N is then divided in the dividing circuit 9 by 2 andfurther processed in the computer 8. Dividing the count N by 2 alreadydetermines the ratio TV in principle between the local oscillator clocksignal IT and the data clock signal DT. This is so because the timespacing between two falling signal flanks corresponds exactly to twodata clock periods DT-1. Thus, the dividing circuit 9 can be consideredto function as a circuit that determines the division ratio TV.

The data interrogation by the interrogator 4 takes place according tothe invention when the count N corresponds exactly to one half of theratio TV between the local oscillator clock signal IT and the data clocksignal DT. As a result, when the synchronization is correct, each databit, is read-out exactly at the time center of its level characteristic.More specifically, each bit is read-out of the bus correctly. Accordingto the invention the division ratio TV is constantly or repeatedlyadapted or updated because particularly the clock signal IT of theinternal oscillator 7 is not known with a sufficient accuracy due tomanufacturing tolerances and due to its variability in response totemperature changes. As a result of such updating, the respectivecurrent or actual value is stored in the memory 6 and not used directlybut it is used after updating to correctly determine the point of timewhen a data interrogation is performed. Using the respective ascertainedcount N directly without updating as a new ratio value could result in asituation where a single error such as a spike S due to a disturbance onthe data bus, please see FIG. 2, could instantly lead to a complete lossof synchronization. The invention avoids this problem by comparing thecount N with the actual current ratio and then updating the currentratio in a step-by-step fashion if necessary as a result of thecomparing.

The updating or adapting of the division ratio is performed by thecomputer 8 in the circuit 1. The computer 8 has a comparator 8 a and anupdating or adapter circuit 8 b. The preferred rules for the adaptationor updating of the division ratio TV has been set forth above and isperformed by the computer 8 preferably in accordance with a givenprogram stored in a memory of the computer 8. Thus, the memory containsthe above mentioned rules. The resulting updated ratio TV′ is yet to bestored in the memory 6. Directly following a reset of the circuitarrangement 1 there is not yet available a ratio TV from the data signalDS. A defined or certain default value is assumed for that case, namelyfollowing directly a resetting.

Thus, according to the invention a correct data interrogation isperformed even if an erroneous adaptation or updating took place, forexample due to a signal error on the data bus. This is so because theadaptation or updating of the ratio TV to TV′ is small in its value fromcycle to cycle. Namely: ΔTV=TV′−TV=±1 (FIG. 1). Moreover, it is anadvantage of the invention that already with the next validsynchronization attempt an updating or adapting error is corrected. As arule, the correction takes place already with the next data bit. As aresult, the method according to the invention has a high tolerancerelative to disturbances on the data bus.

The ascertained count or count value N of local oscillator clock pulsesbetween two falling signal flanks does not need, however, to correspondat all times to two data bits. Thus, respectively higher count valuesare obtained in case several bits with an equal value are counted overseveral clock impulses having a constant signal level. Alternatively,lower values are obtained in case of the above mentioned disturbances onthe data bus. In order to exclude such count values that are too largeor too small for the updating of the ratio TV right from the start, theinvention sets a limit range or value range G for the count N in orderto avoid falsifying the synchronization. This limit range is monitoredby the computer 8. Thus, only if the count N is within the value range G(NEG) an adaptation or updating of the ratio TV is performed. The limitrange G within which the count N is considered to be valid may bedetermined, for example based on the maximum deviations of the localoscillator 7. Assuming a data rate of 2400 bits per second, thefollowing values apply for the local oscillator frequency:TV _(max)=440,000/2400≅183,TV _(rated)=400,000/2400≅167, andTV _(min)=360,000/2400≅150.

In this connection it is necessary to prevent an overrun of the counter5 so that a possibly false count following an overrun cannot beinterpreted as being a valid count.

FIG. 2 illustrates graphically the above described features of theinvention. The signal or rather data signal DS is received, for example,through a bus not shown but connected to the input 2. The count N isavailable at the output of the counter 5 connected to a control input ofthe interrogator 4. The vertical lines symbolize counting events whichare spaced from one another by a time spacing IT⁻¹. The letter G definesthe validity range for the count values N between a minimal valueN_(min) and a maximum value N_(max). This validity range G represents alogic window, so to speak, whereby the level “0” signifies “not valid”and the level “1” signifies “valid”: N_(min/max)=2TV_(min/max).

In the upper part of FIG. 2, the count N is valid between two fallingflanks DSa and DSb of the data signal DS. This count N is used foradapting or updating the division ratio TV to obtain TV′. In the middleportion of FIG. 2 the count N is considered to be invalid due to adisturbance S on the data bus. In the lower part of FIG. 2, the countsare also invalid because of an overflow at the output of the counter 5,resulting in “N_(OF)”. Such invalid counts must be excluded by thecomputer 8 shown in FIG. 1.

FIG. 3 shows a flow diagram illustrating the performance of the presentmethod. A starting step S1 is followed by a cyclical interrogation stepS2 to see whether a clock signal of the local oscillator 7 has beenreceived by the counter 5. As soon as this is the case as indicated bythe letter j, step 3 is performed to see whether a data signal on thebus or at the input 2 has a falling flank. If this is the case as againindicated by the letter j, the step 4 is performed by temporarilystoring the count N in the memory 6. In the next step 5 the counter 5 isset to 0 again. Thereafter, the present method is performed bycontinuing with step 2 and so forth.

If the interrogation in step 3 is negated n, step 6 is performed for afurther interrogation to see whether the count N is smaller than theoverflow count N_(OF) thus: N<N_(OF).

If this is the case as indicated by the letter j, the count N isincremented by the value 1 in step 7. Thereafter, the method iscontinued with step 2 as indicated at B. In case the interrogation instep 6 is negated (n), no incrementation is performed and the operationis continued with step 2.

When step 5 is properly completed, the operation is continued at A withstep 8 in the computer 8 for adapting or updating the ratio TV, wherebyfirst step 8 involves a further cyclical interrogation whether a localoscillator 7 signal has been received. If this receipt is confirmed aspositive j, step 9 is performed, whereby further interrogations are madeto see whether the count temporarily stored in the memory 6 is withinthe valid or permissible range G. More specifically to see whetherN_(min) is smaller or equal to N, which in turn is smaller or equal toN_(max): thus N_(min)≦N≦N_(max). A check is made to see whether therespective value has not yet been taken into account.

In case the response to all interrogations is positive j, step S10compares the value N with the actually valid ratio TV temporarily storedin the memory 6. Depending on the result of the comparing N/2<TV orN/2=TV, or N2>TV any one of the steps S11, S11′ or S11″ is performed forthe adapting or updating of the division ratio TV′=TV−1 or TV′=TV orTV′=TV+1. Thereafter, the above described sequence of steps is repeatedautomatically starting at point “B”.

Thus, the adapted or updated division ratio TV′ is taken over always atthe end of a data bit or at the beginning of a new bit. Care must betaken that the division ratio TV does not change in the center of a bit.Otherwise a double interrogation is possible, namely at the precedingratio TV and at the updated ratio TV′.

Although the invention has been described with reference to specificexample embodiments, it will be appreciated that it is intended to coverall modifications and equivalents within the scope of the appendedclaims. It should also be understood that the present disclosureincludes all possible combinations of any individual features recited inany of the appended claims.

1. A method for synchronizing an operation of a function unit with apredetermined first clock frequency or signal of a received impulsesignal (BS), said method comprising the following steps: a) generating alocal oscillator second clock frequency or signal in said function unit;b) counting cycles of said second local oscillator signal betweenpredetermined impulse flanks of said received Impulse signal to providea count (N); c) dividing said second clock frequency of said leveloscillator by said count (N) to provide a first ratio; d) comparing saidfirst ratio with a predetermined second ratio (TV) to provide acomparing result; and e) adapting or updating said predetermined secondratio (TV) in response to said comparing result to provide an adapted,updated ratio (TV′) for said synchronizing.
 2. The method of claim 1,wherein said step of adapting is performed in accordance with thefollowing rules:TV′=TV+1, for N/2>TV;TV′=TV−1, for N/2<TV;TV′=TV, for N/2=TV; wherein: TV is said predetermined second ratio,wherein: TV′ is said adapted updated ratio, and wherein: N is saidcount.
 3. The method of claim 1, wherein said predetermined impulseflanks of said received impulse signal (DS) between which said countingstep is performed, are two respective falling impulse flanks.
 4. Themethod of claim 1, wherein said predetermined impulse flanks of saidreceived impulse signal (DS) between which said counting step isperformed, are two respective rising impulse flanks.
 5. The method ofclaim 1, further comprising resetting said count (N) in response toreaching a second impulse flank of said predetermined impulse flanks,and storing said updated ratio (TV′) in a memory to provide an updatedratio as the next predetermined ratio (TV′).
 6. The method of claim 1,further comprising establishing a validity range (G) for said count (N),monitoring whether said count (N) is within said validity range (G),generating a control signal when said count (N) is outside said validityrange and preventing said adapting step in response to said controlsignal.
 7. The method of claim 1, further comprising performing saidsteps a, b, c, d and e continuously during a duration of a transmissionand reception of said impulse signal (DS).
 8. The method of claim 7,wherein said steps a, b, c, d and e are performed continuously duringsaid duration of a data transmission and reception.
 9. A circuitarrangement for synchronizing an operation of a function unit with afirst clock frequency (DT) of a transmitted impulse signal (DS) receivedby said function unit (4), said circuit arrangement comprising a counter(5) having a first input (2) for receiving said transmitted impulsesignal (DS) and a second input (2′), a local oscillator (7) operativelyconnected to said second input for generating a second clock frequency(IT) for supplying to said second input (2′) of said counter (5), saidcounter (5) being adapted for counting cycles of said second clockfrequency (IT) between predetermined flanks (SDa, SDb) of impulses ofsaid impulse signal (DS) to provide a count (N), a determinator (9) fordetermining a first ratio (N/2) between said first clock frequency (IDT)of said transmitted impulse signal (DS) and said second clock frequency(IT) of said local oscillator (7), a comparator (8 a) for comparing saidfirst ratio (N/2) with a predetermined second ratio (TV) to provide acomparing result, and an adapter (8 b) for updating said predeterminedsecond ratio (TV) in response to said comparing result to provide a newupdated ratio (TV′) for use as the next predetermined ratio for saidsynchronizing.
 10. The circuit arrangement of claim 9, wherein saidadapter (8 b) performs its updating function in accordance with thefollowing rules:TV′=TV+1, for N/2>TV;TV′=TV−1, for N/2<TV;TV′=TV, for N/2=TV; including the definitions of TV, TV′ and N.
 11. Thecircuit arrangement of claim 9, wherein said counter (5) is adapted tocount said cycles of said second clock frequency (IT) between any one ofa pair of rising impulses of said impulse signal (DS) and a pair offalling impulses of said impulse signal (DS).
 12. The circuitarrangement of claim 9, further comprising a memory (6) operativelyconnected to said adapter (8 b) for temporarily storing said updatedratio (TV′) for use as the next predetermined ratio.
 13. The circuitarrangement of claim 9, further comprising a computer (8) including saidcomparator (8 a) and said adapter (8 b), wherein said comparator isadapted for providing a control signal to said adapter to prevent anupdating of said predetermined second ratio (TV) when said controlsignal signifies that said count is outside a valid count range (G). 14.The circuit arrangement of claim 13, wherein said comparator (8 a)comprises a first threshold circuit for eliminating a count that issmaller than a first threshold, and a second threshold circuit foreliminating a count that is larger than a second threshold.
 15. Thecircuit arrangement of claim 9, wherein said function unit comprises aninterrogator circuit (4) having a first input connected to said input(2) for receiving said transmitted impulse signal (DS) and an output (3)forming an output of said function unit, said interrogator circuit (4)having a second control input connected to a control output of saidcounter (5) for receiving said updated ratio (TV′) as a closed loopcontrol signal for said synchronizing.